1. Field of the Invention
The invention relates to a socket for electrically interconnecting a stack of integrated circuit chips in a single package.
2. Prior Art
Sockets are known for multi-level stacking of integrated circuit packages. For example, U.S. Pat. No. 4,080,026 to Gianni discloses a socket for stacking dual in-line packages (DIP's) to provide an increased memory capacity without increasing the area covered on a printed circuit board. These dual in-line packages comprise an integrated circuit chip interconnected to a thin metal strip, or leadframe, having a network of wires which define leads for the integrated circuit chip. The chip is totally enclosed in an overmolded dielectric body, and leads of the leadframe are partially enclosed within the body and extend therefrom. The dielectric body generally includes top and bottom surfaces, and .side and end walls. The leads extend outwardly from the side walls and bend downwardly. The socket taught by Gianni has metallic contact members that receive the leads from the DIP's that are stacked within the socket. The contact members extend from a bottom of the socket and engage an associated printed circuit board to which they are soldered. In the socket taught by Gianni, the contact members are retained individually in the socket, thus causing manufacturing and handling difficulties.
U.S. Pat. No. 4,696,525 to Coller et al. discloses a socket for stacking integrated circuit packages wherein the contact members of the socket are formed in a leadframe and the socket housing is overmolded around the leadframe, thus taking advantage of leadframe technology to simplify manufacture of the socket. The socket is particularly adapted for stackably interconnecting two small outline J-lead (SOJ) integrated circuit packages. However, Coller et al. do not teach a .socket for stackably interconnecting more than two integrated circuit packages.
Other sockets for stackably interconnecting integrated circuit packages are known. See, for example, U.S. Pat. Nos. 4,116,519 (Grabbe et al.); 4,312,555 (Donaher et al.); 4,398,235 Lutz et al.); and 4,406,508 (Sadigh-Behzadi). Each of these patents discloses a socket for stacking standard chip carrier configurations such as DIP, SOIC, SOJ, and square packages.
The electronics industry experiences constant demand for further miniaturization of electronic components and their associated packaging. While each of the above references solves problems associated with stacking of chip carriers in order to reduce area required on a printed circuit board, further miniaturization requires that height of the stacked integrated circuit chips be reduced as well. The prior art stacking devices are adapted for stacking standard chip carriers, and the resulting package of stacked chip carriers has a minimum height which is equal to the sum of the heights of all of the chip carriers in the stack. There is a need for a device which will enable stacking of individual integrated circuit chips in a vertical array in order to provide a memory chip package having reduced overally height while maintaining the same memory capacity as the prior art devices.
Further, the chip carriers are typically retained in the prior art sockets by frictional engagement of the leads extending from the chip carriers. The leads must be of sufficient size and strength to withstand the frictional engagement without permanent deformation or breakage. For the DIP, SOIC, and SOJ chip carriers, the leads extend downwardly to below the overmolded body of the chip carrier. It would be advantageous for reduction of stacked height if the leads could be fashioned as thin strips extending outwardly from side edges of the chip and parallel to the chip. The prior art sockets are not suitable for electrically interconnecting chips having such leads. The present invention provides a socket for stacking a plurality of individual integrated circuit chips in a vertical array when the chips are attached to leadframes which define thin leads extending outwardly in a plane.